The present invention relates to a semiconductor device and a testing method therefor. More specifically, the present invention relates to the structure of portion of a semiconductor substrate that is subject to stress and a testing method for detecting damage to that portion. The present invention is adapted to detect damage that occurs within the substrate of a semiconductor chip which is subject to mechanical stress when it is packaged into a casing.
In recent years, as integrated circuits advance in miniaturization of chip design rules and functionality, the margin of manufacture generally tends to decline. In particular, the periphery of bonding pads is directly subjected to mechanical shocks by the bonder during the bonding step after a semiconductor chip is placed in a casing. Depending on the material and structure of the semiconductor chip, cracks may be induced in the chip immediately below the bonding pads.
FIG. 1 is a fragmentary plan view illustrating an arrangement of bonding pads of a conventional LSI chip and FIG. 2 is a sectional view illustrating the occurrence of a crack immediately below a pad.
In FIG. 1, 81 denotes an internal circuit area of the LSI chip, 82 a peripheral area (input/output area) of the chip, and 83 an area where the pads are arranged.
In FIG. 2, 90 denotes a semiconductor substrate, 92 a field oxide film, 92 an interlayer insulating film, 93 a pad formed on the interlayer insulating film, 94 a passivation film, and 95 a crack.
The operating speed of MOS devices shows a tendency to have reached the top because of an increase in parasitic resistance due to shallow source-drain junctions and velocity saturation of carriers. As a countermeasure, an attempt has been made to use low-resistivity Cu interconnections and low-dielectric-constant interlayer insulating films.
It has been reported that, when a low-dielectric-constant interlayer insulating film is used, a failure of Cu interconnections peeling off the insulating film occurs immediately below the pads (Mukul Saran et al., "Elimination of Bond-Pad Damage Through Structural Reinforcement of Intermetal Dielectrics", Proceedings of International Reliability Physics Symposium, 1998, pp. 225 to 231). This failure is a serious problem for the evolution of LSIs.
Heretofore, in order to detect damage that occurred in the substrate below pads, it has been required to disassemble the semiconductor chip and etch the substrate using an etchant such as KOH. With this method, however, a troublesome defect detection processing is needed and it is impossible to detect accurately substrate damage over the whole region of the chip.